1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a transistor and method for forming the transistor by implementing silicidation of transistor unctions prior to forming the transistor gate structure. The gate structure preferably includes a high K value gate dielectric integrated with a metal gate electrode that is capable of withstanding high temperature anneals.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor (MOSFET) device is well known. MOSFETs are generally manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions (i.e., junctions) adjacent to and on opposite sides of the gate conductor. The gate conductor serves to self-align impurities subsequently forwarded into the substrate on opposite sides of the gate conductor. The transistor junctions (i.e., source/drain areas) are therefore said to be self-aligned with the gate conductor.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to increase the switching speed of transistors within the integrated circuits. One method of doing so is to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the gate-to-substrate capacitance.
Threshold voltage V.sub.T of a transistor decreases as the gate-to-substrate capacitance increases. The capacitance per unit area, C.sub.ox, of a gate dielectric can be expressed as: EQU C.sub.ox =.epsilon./t.sub.ox
where .epsilon. is the permittivity the gate oxide and t.sub.ox is the thickness of the gate oxide. The above equation for C.sub.ox demonstrates that the capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric and inversely proportional to the thickness of the dielectric.
By normalizing the permittivity, .epsilon., of a material to the permittivity of vacuum, .epsilon..sub.0, the relative permittivity of a material can be determined. Relative permittivity, or dielectric constant, K, is typically used in place of permittivity. The dielectric constant of a material is defined as: EQU K=.epsilon./.epsilon..sub.0
Silicon dioxide ("oxide") has a relatively low K of approximately 3.7 to 3.8. Consequently, the minimum value of V.sub.T, and thus the transistor switching speed, is limited by the need to maintain a certain gate oxide thickness in order to promote capacitive coupling between the gate conductor and the substrate.
Because of the relationship between gate oxide thickness and threshold voltage, conventional transistors typically include an ultra thin gate oxide to increase the gate-to-substrate capacitance, and thereby lower V.sub.T. The value of the gate-to-source voltage, V.sub.GS, required to invert the channel underneath the gate conductor such that a drive current, I.sub.D, flows between the source and drain regions of the transistor is decreased. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing such transistors is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, thin oxide films may break down when subjected to an electric field. Particularly, for a gate oxide that is less than 50 .ANG. thick, it is probable that when V.sub.GS is equivalent to only 3V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. Consequently, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, V.sub.T may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of V.sub.GS because of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to the unevenness at which the oxide grows on a less than perfect silicon lattice. Low breakdown voltages also correlate with high defect density near the surface of the substrate.
Accordingly, the use of a high quality gate dielectric (i.e., one that is resistant to breakdown and has a high K value, etc.) is desired. Because of their high K values, metal oxides are sometimes used as the gate dielectric. Since metal oxides generally have much higher K values than does oxide, a metal oxide gate dielectric can be made thicker than a oxide gate dielectric while maintaining equivalent gate-to-substrate capacitance. Unfortunately, deposited metal oxides are typically not stoichiometric, may contain oxygen vacancies and, overall, are not sufficiently stable to be readily implemented in a production environment. Moreover, precisely depositing a uniformly thin layer of metal oxide is difficult.
In addition, the typical gate electrode is typically made from deposited polysilicon (as stated above). To lower the resistivity of the polysilicon gate, and thus increase the speed of the transistor, it is desirable that the entire polysilicon layer forming the gate be substantially doped. During a conventional transistor formation process, the polysilicon gate is typically doped at the same time as the source/drain areas in order to make the process more efficient. This simultaneous implantation may cause difficulties since the implant depth required for the gate is typically deeper than the desired implant depth of the source/drain areas. Provided spiking does not result, it is desirable to make the junctions (i.e., source/drain areas) as shallow as possible to reduce parasitic junction capacitance and resistance. A desired deeper channel depth takes into account dopants which may segregate and diffuse through the gate dielectric from the overlying gate conductor. Significant amounts of dopant diffusion can cause a threshold skew at the doped channel. Boron commonly used to dope p+ gates readily migrates though thin gate oxides (less than 125 angstroms) under high temperature processes (e.g., annealing at 900.degree. C.). In order to avoid this migration, processing temperatures must be lowered. Such lowering, however, may result in insufficient distribution and/or anneal of the previously implanted dopants.
Furthermore, as the feature size in circuits decreases, the need to decrease the resistance and capacitance and thus the RC delay associated with interconnection paths becomes more urgent. For example, in submicron MOSFETs the interconnect RC delay can exceed delays due to gate switching. Doped polysilicon gates do not provide, by themselves, the low resistivity interconnection paths necessary for the fabrication of dense, high performance devices.
One way in which some of the problems of polysilicon gate conductors may be avoided is by substitution of aluminum for polysilicon. A gate conductor made of aluminum (or another metal) may partially block implant paths and prevent migration of impurities into the channel region. In addition, the greater conductivity of aluminum over polysilicon aids in reducing propagation delay. Unfortunately, the relatively low melting point of aluminum makes its use as a gate conductor undesirable if subsequent processing steps involve temperature cycles greater than approximately 500.degree. C.
After the formation of the gate dielectric and gate electrode, ohmic contacts are typically formed between transistor source/drain regions and overlying interconnect. The formation of self-aligned suicides ("salicides") upon the source/drain regions as contact structures is commonly used to reduce the contact resistance at the contact/junction interface. In this process, oxide spacers placed laterally adjacent to the sidewalls of the gate conductor are often used to electrically separate the gate and source/drain regions. As device dimensions shrink, however, the likelihood of lateral formation of the silicide over the narrow oxide-spacer region increases. This phenomenon is referred to as silicide shorting or bridging.
Bridging can, in some instances, be prevented if the anneal cycle used to form the silicide is carefully controlled. A multiple step salicide formation process is often used for this purpose. In this process, a refractory metal such as titanium is deposited over the entire wafer. The metal film is then heated to a relatively low temperature in the presence of a nitrogen ambient in order to form a relatively high resistivity silicide over the source/drain regions. The lower temperature (&lt;700.degree. C.) helps inhibit cross-diffusion between silicon atoms within the spacers and/or gate conductor and metal atoms within the refractory metal layer. Afterwards, any unreacted metal is etched away, leaving a layer of metal silicide over the source/drain regions. A final, higher temperature anneal is then performed to produce a more stable, lower resistivity silicide.
Unfortunately, there are problems with this two-step annealing process. One problem is caused by removing the silicon substrate from the annealing chamber after the first anneal to etch away the remaining unreacted metal. Withdrawing the substrate from the annealing chamber, unfortunately, allows the growth of native oxides or the deposition of unwanted impurities upon the silicide layer. The presence of such impurities may have the detrimental effect of increasing the resistance of the silicide. Moreover, if the source/drain regions are highly doped, the relative lack of silicon atoms may make it necessary to increase the temperature of the first anneal above a desirable level.
Therefore, it would be desirable to develop a technique for fabricating a transistor that would allow the formation of a highly conductive silicide layer without silicide bridging. In addition, it would be desirable to create a technique that avoids some of the problems caused by a two-step salicide anneal. It would also be desirable to form a transistor that avoids the problems of impurity migration and lower conductivity generally associated with polysilicon gate electrodes, yet can withstand the high temperatures common in many processes (e.g., annealing). Furthermore, it would be advantageous to employ a metal oxide gate dielectric while avoiding the drawbacks of deposited metal oxides. The improved transistor would be one that avoids the problems of very thin oxides, yet provides high-speed operation necessary for modern integrated circuits.